module Memory(iClk, iMemRead, iMemWrite, iAddress, iWriteData, oMemData
,oInst0 ,oData1, oData2, oData5, oData16, oData17 //added for test
);
	input iClk, iMemRead, iMemWrite;
	input [31:0] iAddress, iWriteData; //only the last 8 bits of address is used 
	output [31:0] oMemData;
	
	//Memory data of each address added for test
	//each physical address of these data is added by 128 to avoid collision with instructions.
	output [31:0] oInst0, oData1, oData2, oData5, oData16, oData17; 
	
	reg [31:0] oMemData;

	reg [31:0] Cells[255:0]; //8bit 
	
	always @(posedge iClk)//synchronous write
	begin
		if(iMemWrite)
			Cells[iAddress[7:0]] <= iWriteData;
		

	end

	always @(*)//asynchronous read
	begin
		if(iMemRead)
			oMemData = Cells[iAddress[7:0]];
		else
			oMemData = 32'b0;
	end
	
	//added for test
assign oInst0=Cells[0];
assign oData1=Cells[129];
assign oData2=Cells[130];
assign oData5=Cells[133];
assign oData16=Cells[144];
assign oData17=Cells[145];

endmodule